swap_horiz Sequential Data Storage & Transfer

Shift Registers Laboratory

Interactive virtual simulations of SISO, SIPO, PISO, and PIPO shift registers. Explore bit-shifting mechanics, parallel data conversion, and flip-flop timing diagrams.

4 Modules

100% Available

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AVAILABLE

SERIAL-IN SERIAL-OUT (SISO)

Data is entered serially bit-by-bit and shifted out one bit per clock cycle through 4 D flip-flops.

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call_split

AVAILABLE

SERIAL-IN PARALLEL-OUT (SIPO)

Serial data bits are shifted in sequentially and presented simultaneously on parallel output pins.

Open SIPO Simulation arrow_forward

call_merge

AVAILABLE

PARALLEL-IN SERIAL-OUT (PISO)

Parallel input data is loaded simultaneously on command, then shifted out serially one bit per clock pulse.

Open PISO Simulation arrow_forward

swap_horiz

AVAILABLE

PARALLEL-IN PARALLEL-OUT (PIPO)

Parallel input data is loaded and output simultaneously in a single clock cycle with zero shift delay.

Open PIPO Simulation arrow_forward